The present invention relates to electronic devices, and more particularly, to a smart card reader.
An example smart card reader 1 known as a viewer is illustrated in FIG. 1. A viewer type card reader 1 generally comprises a small size case or housing 2, a display 3 and a slot 4 for receiving the smart card 5. Due to the reduced size of the case 2, only an end of the card 5 is received. This type of reader enables, for example, the number of remaining units in a phone card to be displayed, and the amount of money available in a smart card of the electronic purse type to be displayed. The reader 1 may be in the form of a key ring, as shown in FIG. 1.
As illustrated in FIG. 2, inside of such a reader 1 is generally a printed circuit board 10 on which a microprocessor 11, the display 3, a smart card connector 12, a travel end detector 13, and an electrical battery 14 providing electrical power to the microprocessor 11 are laid out on.
The microprocessor 11 is generally of the microcontroller type and includes on the same silicon chip various peripheral components such as an oscillator, a ROM type program memory, a RAM and/or EEPROM type data memory, and display drive circuits, etc. The connector 12, which is generally a friction type connector, for example, comprises metal pads 12-i configured so that they coincide with the contact pads 5-i of the smart card 5 when inserted in the reader 1.
The travel end detector 13 enables the microprocessor 11 to know whether a card 5 is inserted in the housing to initialize communication with the card. Since there is no protection in this type of reader against the card 5 being pulled out, conventionally, the microprocessor 11 is programmed so that it stops communicating with the card in a clean way, particularly when the card is suddenly removed from the reader. For this, the microprocessor 11 has a few milliseconds during which the metal pads 12-i of the connector 12 are still in contact with the pads 5-i of the card 5. The removal rate of the card 5 is on the order of 2 m/s. Stopping communications in a clean way includes sending a reset signal (RST) to the card 5 according to the ISO 7816 standard, for example.
Operation of reader 1 will now be discussed below. For periods of non-use, the microprocessor 11 places itself in an idle or standby state wherein its consumption is very low. This consumption is typically on the order of 1 to 10 xcexcA according to the structure and complexity of the microprocessor 11.
When a card 5 is inserted into the housing and is at the end of travel therein, the closing of detector 13 triggers an interrupt in the microprocessor 11, which then initializes communication with the card 5 and displays the information contained therein. When the card 5 is removed, the opening of the detector 13 triggers a new interrupt and the microprocessor 11 switches back to the standby state. If the microprocessor 11 is still in communication with the card 5 at the instant of its removal, it interrupts communication with the card before placing itself in the idle state.
The main drawback of such a reader 1 is that it has a non-zero consumption of current when not in use, and a limited battery life time. Since the period of use of the reader 1 is insignificant with respect to the period of being idle, the consumption of the microprocessor 11 in the idle state, although minimal, has a significant influence on the life of the battery 14.
A smart card reader comprising a system for reducing the electrical power supply of the reader when a smart card is removed therefrom is disclosed in European Patent No. 762,307. This system comprises a switch detecting the presence of a smart card, which delivers an active signal to a circuit providing the power supply voltage for the reader. The system stops delivering the electrical power to the reader when this signal is emitted. However, the system requires a certain degree of complexity for having the power supply circuit react to the active signal delivered by the card detector.
A microprocessor provided with a system for detecting power supply voltage drops is also disclosed in U.S. Pat. No. 5,428,252. The power supply voltage is provided by a battery, and the detection system delivers an interrupt signal for a large drop in the power supply voltage. The interrupt signal enables the microprocessor to back up data before switching over to a sleep mode. Moreover, European Patent No. 803,831 describes a smart card reader comprising two switching means, one for activating the reader when a card is inserted therein and the other for detecting card removal to allow the reader to finish a current transaction.
An object of the present invention is to provide a straightforward and low cost approach for suppressing power consumption of a microprocessor in a smart card reader when a smart card is not in the reader.
Another object of the present invention is to suppress power consumption of the microprocessor while being able to properly interrupt communication with a smart card when the card is abruptly removed.
These objects are achieved by providing a smart card reader comprising a housing for receiving a smart card, a microprocessor, means for connecting the microprocessor to the smart card inserted in the housing, a voltage source, and means for not delivering to the microprocessor the voltage provided by the voltage source when the smart card is not in the housing. The means for not delivering to the microprocessor the voltage provided by the voltage source comprises a first switching means of the normally open type, interposed between the voltage source and a power supply terminal of the microprocessor. The first switching means is configured to close when a card is at the end of travel in the housing, and is configured to open when the card is no longer at the end of travel.
According to one embodiment, the microprocessor comprises means for detecting the opening of the first switching means, means for ending communication with a smart card if the first switching means opens during such a communication, and a capacitor for maintaining the power supply voltage of the microprocessor above a threshold when the first switching means switches from the closed state to the open state. This is done at least during the time necessary for the microprocessor to end a current communication.
According to one embodiment, the means for detecting opening of the first switching means comprise a comparator for comparing the power supply voltage of the microprocessor with a reference voltage. The reference voltage may be generated by the voltage delivered by the voltage source without passing through the first switching means. The reference voltage may be delivered by a voltage divider powered by the voltage source. The voltage divider may be connected to ground by a switch that is in the open state when the microprocessor is not powered.
According to one embodiment, the means for ending a communication comprise means for generating an interrupt signal when the comparator output changes its value as a result of the opening of the first switching means. The means for detecting an opening of the first switching means may comprise a second switching means that closes when a card is at the end of travel in the housing, and opens when the card is no longer at the end of travel in the housing. The second switching means has a first terminal connected with the voltage source, and a second terminal monitored by the microprocessor. The means for ending a communication may comprise means for generating an interrupt signal when the second switching means switches from the closed state to the open state.
The present invention also relates to a comparator including two input branches each comprising at least one ballast transistor and a control transistor for receiving the aforementioned power supply voltage and reference voltage. For example, the comparator may comprise an additional ballast transistor connected in parallel with a ballast transistor of one of the input branches, and means for connecting the control input of the additional ballast transistor to the control inputs of the other ballast transistors when the output voltage of the comparator is in a first state.
The comparator may further comprise means for blocking the additional ballast transistor when the output voltage of the comparator is in a second state. The comparator has a switching hysteresis depending on the state of its output. According to one embodiment, the comparator further comprises means for causing the additional ballast transistor to conduct during a transition period when the output voltage of the comparator switches from the second state to the first state.
The comparator may further comprise means for blocking the ballast transistors during a transition period when the output voltage of the comparator switches from the first state to the second state. The means for blocking or for causing the additional ballast transistor to conduct during a transition period may comprise means for delaying, during the transition period, the application of control signals that depend on the new state of the output of the comparator to the additional ballast transistor.